Wiki says you are right.
Unfortunately also like you it tells us what it is not rather than what it is.
The 5 nanometer ( 5 nm ) lithography process is a technology node semiconductor manufacturing process following the 7 nm process node. … The term " 5 nm " is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor…
Maybe it’s a bit like 5G.
5G is revolutionary but as far I can tell it’s a bunch of tech all lumped together that enables that breakthrough.
OK … for those who are interested, I think I might have got to the bottom of the “process node” business. The designator ‘5’ or ‘7’ or whatever is indeed just a descriptor for the density/speed/power characteristics of the devices being constructed, and they represent a whole package of technologies, not just device scaling. There is therefore some overlap between what some manufacturers call (say) 10nm and what others will call 7nm, and there are many process variants at any given node. When you’re describing things that small, it’s not really surprising.
These numbers used to refer to the gate width of a MOSFET. However MOSFETs in ICs are no longer simple planar structures. The usual type these days seems to be a FinFET, which is a 3D arrangement with the gate wrapped around the channel. The “5nm” or “7nm” designation for the process correlates with the fin width, although not precisely so.
So, as I suspected, the number refers to the bare-minimum size of some primitive structure that can be reliably etched out of a chunk of silicon.
Going from 5nm->3nm, it looks like a different structure will be used to achieve an equivalent density scaling; it seems unlikely that the channel width will actually be 3nm.
There’s nothing actually 5nm. not even fin width. As I said, its highly academic, it’s not easy to explain it without the background. 3D FETs have been around for a while now and the “fins” are just an approximation - there’s nothing that’s actually designed as a 5nm there.
Simply saying: Stop reading too much into the number for the process nodes. It doesn’t mean anything by itself.
Well, that really isn’t true. According to that article, there’s a density increase at each process node which is equivalent to a linear feature shrink of (say) 7->5nm, even if that density increase isn’t driven by a linear feature shrink.
No, you’re wrong. Again you’re reading too much into the number. One company’s 7nm may mean a certain density. But another’s could mean the same density with a different number.
You’re trying to make it too simplistic, but unfortunately, its not so. Please read academic papers in full to understand the details.
Here’s a rough comparison to outline the point I made above:
See the chart for 7nm density comparison. It’s equivalent to Intel’s “10nm” node. So just because a process goes from 10nm->7nm, doesn’t “necessarily” mean anything in simplistic terms.
It’s just not easy to lay it out in simple terms. That’s why I’m saying just think of it as marketing terms (which is true, since after 2000, driven by Intel, it was the marketing guys which had the decision making power to brand these and not engineers)
Apple accounts for 1/5 of their sales. If they make 17,000 per water for Apple, even if they make zero for everyone else, thats $3400 per wafer average.
We have created a new manufacturing process with smaller features and tighter tolerances. In order to achieve this goal, we have integrated new manufacturing technologies. We refer to this set of new manufacturing technologies as a process node because we want an umbrella term that allows us to capture the idea of progress and improved capability.”
In terms of 15 year timelines it’s similar to the biotech industry somewhat, probably because of the quality standards and investment required.
So it’s not really nanometers, just nanomarketing? Why would the “marketing guys” at Intel announce then that Intel has been stuck at 14nm mode while its competitors are already nanomarleting “5nm technology? Is that just a clever marketing ploy?
This has happened in the face of chip manufacturers TSMC in Taiwan and Samsung in South Korea moving to 5-nanometer processes this year—enabling them to create denser, more efficient computer chips—while Intel “has been stuck at its 14nm node since 2013” and will be “several years behind its Asian peers” until at least 2025 with its recent 7nm issues, according to Loeb.
